Linux Foundation to Host CHIPS Alliance Project to Propel Industry Innovation Through Open Source Chip and SoC Design
Mar 12, 2019
*New Linux Foundation Project to Foster Flexible, Next-Generation Chip Design for Diverse Data-Centric Applications and Workloads *
SAN FRANCISCO – March 11, 2019 – The Linux Foundation , the nonprofit organization enabling mass innovation through open source, today announced its in tent to form the CHIPS Alliance project to host and curate high-quality open source code relevant to the design of silicon devices. CHIPS Alliance will foster a collaborative environment that will enable accelerated creation and deployment of more efficient and flexible chip designs for use in mobile, computing, consumer electronics, and Internet of Things (IoT) applications.
Early CHIPS Alliance backers include Esperanto Technologies, Google, SiFive and Western Digital, all committed to both open source hardware and continued momentum behind the free and open RISC-V architecture .
“The RISC-V community is working to foster open source foundation technologies that will help unlock market innovation to move [ artificial intelligence/machine learning and infrastructure composability] forward,” said Eric Burgener, research vice president of IDC’s Infrastructure Systems, Platforms, and Technologies Group, via a recent IDC report .
The project will create an independent entity so companies and individuals can collaborate and contribute resources to make open source CPU chip and system-on-a-chip (SoC) design more accessible to the market.
“Open collaboration has repeatedly proven to help industries accelerate time to market, achieve long-term maintainability, and create de facto standards,” said Mike Dolan, vice president of strategic programs, the Linux Foundation. “The same collaboration model applies to the hardware in a system, just as it does to software components. We are eager to host the CHIPS Alliance and invite more organizations to join the initiative to help propel collaborative innovation within the CPU and SoC markets.”
“As new workloads surface every day, we need new silicon designs in order to optimize processing requirements,” said Martin Fink, interim CEO of RISC-V Foundation and executive vice president and CTO of Western Digital. “Today’s legacy general-purpose architectures are, in some cases, decades old. With the creation of the CHIPS Alliance, we are expecting to fast-track silicon innovation through the open source community.”
CHIPS Alliance will follow governance practices consistent with other Linux Foundation projects, which will include a Board of Directors, a Technical Steering Committee, and community contributors who will work collectively to manage the project. Initial plans will focus on establishing a curation process aimed at providing the chip community with access to high-quality, enterprise grade hardware.
Google is planning to contribute a Universal Verification Methodology (UVM)-based instruction stream generator environment for RISC-V cores. The environment provides configurable, highly stressful instruction sequences that can verify architectural and micro-architectural corner-cases of designs.
SiFive was founded by the inventors of the free and open RISC-V Instruction Set Architecture, who, together with their colleagues at UC Berkeley, developed the first opensource RISC-V microprocessors and a new opensource hardware description language Chisel. This initial work at UC Berkeley also developed the RocketChip SoC generator, including the initial version of the TileLink coherent interconnect fabric.
SiFive remains committed to maintaining and improving the RocketChip SoC generator and the TileLink interconnect fabric in opensource as a member of the CHIPS Alliance, and contributing to Chisel and the FIRRTL intermediate representation specification and transformation toolkit. SiFive will also contribute and maintain Diplomacy, the SoC parameter negotiation framework.
Western Digital is planning to contribute their high performance, 9-stage, dual issue, 32-bit SweRV Core, together with a test bench, and high-performance SweRV Instruction set simulator. Additional contribution will be specification and early implementations of OmniXtend cache coherence protocol.
To learn more about CHIPS Alliance, p lease visit www.chipsalliance.org .