Design period reduced by up to 98%

Tokyo, June 2, 2016 - NEC Corporation (NEC; TSE: 6701) today announced that it has developed a data communications method for a heterogeneous device to achieve rapid communications between a CPU and FPGA on a tightly coupled processor (Co-Packaged CPU + Field Programmable Gate Array [FPGA]).

The Internet of Things (IoT) requires high-performance processors for the high-precision analysis of the massive amounts of data transmitted from sensors and devices. In recent years, tightly coupled processors featuring two types of computing devices – a central processing unit (CPU) and an FPGA – have been gaining greater attention as high-performance processors.

The new methodological model developed by NEC eliminates the need to modify software on a CPU and can shorten the design period of IoT applications by up to 98% when compared to conventional methods. This is accomplished by making full use of a tightly coupled processor's ability to facilitate an FPGA's access to data on a CPU. NEC removes the need to modify software on a CPU through an FPGA's direct reading and writing of data on a CPU.

In addition, the new methodological model can accelerate communications by optimizing data communications units. An FPGA's comprehensive access to data on a CPU improves the utilization of the broadband transmission path of a tightly coupled processor. Additionally, an adjustment of the data communications units in accordance with the data size and required performance of a target application enables faster communications for a wide range of applications. This can significantly reduce the time and effort for tuning the performance of high-precision analysis in sync with the data processing of an application.

"NEC evaluated this method with an experimental model of Intel's CPU-FPGA tightly coupled processor. The combination of this new method with NEC's semiconductor design tool, CyberWorkBench, enabled us to shorten the design period of an IoT application on a CPU-FPGA tightly coupled processor by approximately 98%," said Yuichi Nakamura, General Manager, System Platform Research Laboratories, NEC Corporation.

NEC will unveil the technology on June 7 at the Design Automation Conference (website at http://dac.com/) in Austin, Texas, from June 5 to 9.